1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly to a circuit and method for controlling entry to a test mode of the semiconductor memory device.
2. Discussion of the Related Art
Generally, a semiconductor memory device includes a test mode so that test functions can be performed by the device manufacturer. To perform the test functions, such as those associated with the reliability of the semiconductor memory device, the device is placed in a test mode.
The test mode is an operating mode that is specifically used to test the semiconductor memory device. The functions of the test mode are not controlled by a user except for certain mode register set (MRS) commands for controlling device settings. For example, MRS commands such as column address strobe (CAS) latency or burst length may be controlled by the user.
A semiconductor memory device typically includes a test mode entry circuit for controlling entry to the test mode based on a particular address and/or command combination. A conventional test mode entry circuit will now be described with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram illustrating a conventional test mode entry circuit.
Referring to FIG. 1, the test mode entry circuit includes an address buffer unit 110, a first address sampling unit 120, a second address sampling unit 130, a first flip-flop 140, a second flip-flop 150, a clock buffer unit 160 and a delay unit 170.
The address buffer unit 110 receives and buffers an address Ai and outputs a buffered address TAi.
The first address sampling unit 120 samples the buffered address TAi using a buffered clock PCLK to activate a first address combination signal PAi1 based on a predetermined address combination.
The second address sampling unit 130 samples the buffered address TAi using the buffered clock PCLK to activate a second address combination signal PAi2 based on a predetermined address combination. It is typically desirable to generate the first and second address combination signals PAi1 and PAi2 from different address combinations.
The first flip-flop 140 samples the first address combination signal PAi1 based on a delayed clock PCLKP to generate a first test mode entry signal TENT1.
The second flip-flop 150 samples the second address combination signal PAi2 based on the delayed clock PCLKP to generate a second test mode entry signal TENT2.
A test mode is entered in response to the first and second test mode entry signals TENT1 and TENT2. For example, when the first and second test mode entry signals TENT1 and TENT2 are successively activated, a semiconductor memory device including the test mode entry circuit enters the test mode.
As further shown in FIG. 1, the clock buffer unit 160 buffers an input clock CLK to generate the buffered clock PCLK.
The delay unit 170 receives and delays the buffered clock PCLK by a predetermined period of time to generate the delayed clock PCLKP. The first and second address combination signals PAi1 and PAi2 are sampled using the delayed clock PCLKP so that the first and second test mode entry signals TENT1 and TENT2 are stably generated.
Although not shown in FIG. 1, in addition to the two test mode entry signals TENT1 and TENT2, a command combination signal generated by a command combination it may also be used to perform the test mode entry.
FIG. 2 is a timing diagram illustrating an operation of the test mode entry circuit in FIG. 1.
Referring to FIG. 2, a first address combination Ai_ent1 and a second address combination Ai_ent2 are externally inputted, alternating once every two clock periods.
A buffered clock pulse PCLK is generated in every period of the externally provided input clock CLK.
The first address combination Ai_ent1 is sampled at a rising edge of a first buffered clock PCLK to activate a first address combination signal PAi1.
At a next rising edge of a second buffered clock PCLK, an address Ai does not correspond to either the first address combination Ai_ent1 or the second address combination Ai_ent2, so that neither the first address combination signal PAi1 nor the second address combination signal PAi2 is activated.
At a next rising edge of a third buffered clock PCLK, the second address combination Ai_ent2 is sampled to activate the second address combination signal PAi2.
At a next rising edge of a fourth buffered clock PCLK, the address Ai does not correspond to either the first address combination Ai_ent1 or the second address combination Ai_ent2, so that neither the first address combination signal PAi1 nor the second address combination signal PAi2 is activated.
The first and second address combination signals PAi1 and PAi2, each having an active state, are sampled using a clock PCLKP delayed from the buffered clock PCLK by a predetermined time period to generate the first and second test mode entry signals TENT1 and TENT2.
As shown in FIG. 2, the buffered clock PCLK has a rising edge in every period of the external clock CLK, and the first and second address combination signals PAi1 and PAi2 are sampled using the delayed clock PCLKP, delayed from the buffered clock PCLK, so that the first and second address combination signals PAi1 and PAi2 are sampled in every period of the external clock CLK.
Therefore, sampling of the address combination signals PAi1 and PAi2 should be completed before the address combination signals PAi1 and PAi2 are changed at a next rising edge of the buffered clock PCLK. This results in a decrease in a timing margin MG that corresponds to a time interval between a rising edge of the delayed clock PCLKP and a rising edge of the buffered clock PCLK.
When the timing margin MG between the rising edge of the delayed clock PCLKP and the rising edge of the buffered clock PCLK is decreased, certain functionalities of the test mode entry circuit may be affected. In addition, the timing margin MG is decreased as an operating frequency of a semiconductor memory device is increased. Thus, the timing margin MG is an important consideration when designing a semiconductor memory device including the test mode entry circuit.
For example, when the timing margin MG is decreased to zero, the address combination signals PAi1 and PAi2, which are to be sampled by the delayed clock PCLKP, may transition so that a hold time and a setup time for generating the test mode entry signals TENT1 and TENT2 may be difficult to secure. Therefore, a need exists for a circuit and a method that enable a semiconductor memory device having a high operating frequency to safely enter a test mode.